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Summarize s Relaxing , Uncensored , Groundbreaking …. The Dr . Wang’s original lecture: s s i9000 s h s Guide of Design and style Compiler t s Introduction Setting Up the Tutorial Graphic Interface The Alarm Clock Design Setting Style Environment Environment Design Constraints Overview of Optimization Phases Evaluation of Report DC Tutorial , two Introduction h s t Introduction s i9000 s s s The Synthesis Procedure Design Compiler Products Activity Programs and Tools Style Styles Output and input Formats Consumer Interfaces Screenplay Files DC Tutorial , 4 The Synthesis Process

Start Spin Verilog Code Read in Design Established Attributes Established Realistic Timing Goal Examine Design Mistakes No Certainly Fix Insects Change Restrictions Modify Make Attributes Ungroup Design Prevents The DC Products t DC Professional – Not any multi-frequency clocking, latch-based period borrowing, pipeline re-timing, important path resynthesis, in-place search engine optimization, and gradual editing s i9000 DC Expert – Consist of features intended for maximizing efficiency s FPGA Compiler – Targets simply FPGA technology Optimize No real? Yes Completed DC Tutorial , five DC Guide , 6 1 Synthesis Tools HDL Design Analyzer HDL Compilers DesignWare DesignWare Developer

Architectural Optimization s i9000 s System Optimization Gate-Level s s i9000 Design Analyzer Logic Marketing Design Compilers Cell Collection Library Compiler s h Arithmetic Marketing Timing and Area-Based Source Sharing Sub-expression Removal Constraint-Driven Resource Selection Inference of Synthetic Component (DesignWare) For additional information – HDL Compiler for Verilog Reference Manual Maximized Gate-level Netlist DC Article , several DC Tutorial , 8 DesignWare s i9000 DesignWare Programmer Provide a selection of high-level design pieces – Adders, Multiplier, etc .

s s

The HDL compiler will certainly select the proper components for you personally based on the timing and area desired goals See Documents Collection (open collection) – Synopsys DesignWare 1997. 01 s Generate DesignWare Your local library DC Tutorial , on the lookout for DC Training , 12 DC Items s Cellular Library h Library of basic cells used by POWER – AND, OR, XOR, etc . s Optimize the design with the gate level Using picked cell libraries s Intended for FPGA compiler, it may include more complex cellular material – Xilinx CLBs, IOBs, etc . DC Tutorial , 11 POWER Tutorial , 12 2 Library Compiler Design Designs s Yes, you can make your own cellular libraries t s Hierarchical or Trim Combinational or perhaps Sequential

POWER Tutorial , 13 DC Tutorial , 14 Type Formats s s s s Outcome Formats s i9000 s t s h VHDL Verilog PLA , EDIF 2 . 00 Xilinx XNF t Synopsys binary format (. db files) VHDL Verilog EDIF 2 . 00 Equation, LSI Reasoning, Mentor Design, PLA, condition table, Tegas formats Xilinx XNF file format DC Guide , 12-15 DC Tutorial , 16 User Interfaces s Intrigue s shell&gt, dc_shell – – – – – – – – – unix-like order shell dc_shell&gt, quit dc_shell&gt, cd my_dir dc_shell&gt, alias wv write -f verilog dc_shell&gt, pwd dc_shell&gt, record n dc_shell&gt, list -command dc_shell&gt, gentleman dc_shell&gt, sh “lpr ” s s s s shell&gt, design_analyzer graphical software DC Training , 17 A set of order can be put together into a data file called “script” Then, you don’t need to re-type a few the orders again and again with all the dc_shell Pi�ce for this article will be provided for your reference point You can manage them when you are home with no X-window capacity DC Tutorial , 18 3 Locate Documentation t s h s s s s i9000 shell&gt, design_analyzer , choose Help , &gt, On the web Documentation …. Ignore the square window with “Titles” – select Cancel to close this – give attention to the one with “File, Change, View …” select File , &gt, Open Collection select Synopsys Synthesis Equipment 1997. one particular and then click OK select Documents Set up for Stamping and then simply click Open In the “File, Modify, View …” window, you can now select a set of on-line files DC Training , nineteen Setting Up the Tutorial Creating the Training s h s t Creating The Directories s &gt, cp -r /baby/synopsys/doc/syn/tutorial. House Directory article Creating the web directories Setting pathways and aliases Creating a start up file Running tutorial with scripts db/ verilog/ vhdl/ appendix_A/ Program files work (empty) POWER Tutorial , 21 POWER Tutorial , 22 Route s t. synopsys_dc. installation file %&gt, source /usr/local/bin/setup. synopsys Or perhaps you can input it in. cshrc file – %&gt, supply. cshrc – %&gt, rehash s s i9000 You can take a peek of the installation file – %&gt, more /usr/local/bin/setup. synopsys s Making a. synopsys_dc. setup file may overwrite program default settings %&gt, cp ~/tutorial/. sysnopsys_dc. setup ~/. synopsys_dc. set up %&gt, mire ~/. synopsys_dc. setup – company sama dengan “Motorola Somerset”, – designer = “CEO”, – view_background = “while”, s That basically create the right environmental variables for you DC Guide , 3 DC Training , twenty-four 4

Even more about set up file s i9000 Scripts t s %&gt, more. synopsys_dc. setup – search_path = + search_path – link_library … target_library … symbol_library … define_design_lib … s t s s i9000 s search_path = a directory + search_path – should you cp training into a index other than house link_library: location of subdesgins referenced by design target_library: identify technology libraries symbol_library: identify symbols library to get generating/viewing schematics define_design_lib: discover a temporary destination to store advanced files made by the analyzer DC Tutorial , twenty-five No X-Window, No Problem Get script data files in ~/tutorial/appendix_A/. See Style Analyzer Guide Manual for more detail DC Tutorial , 26 Graphic Interface t s Commence: %&gt, design_analyzer , Stop: Select File , &gt, Quit Menu Bar Visual Interface Look at Buttons Level Buttons Scroll Bar Meaning Area (view_background = “while”, ) Perspective Window POWER Tutorial , 28 Mouse button Buttons t Check Standard Setup s Setup , &gt, Fails , Still left Button – Select design and style and design and style objects s i9000 Mid Switch – Add or remove objects by a group of items already chosen s Proper Button Bring up the pop-up menu POWER Tutorial , 29 POWER Tutorial , 30 5 Read in a Design s i9000 Save a Design s File , &gt, – analyze , elaborate – read Document , &gt, Save or Save As … – Once a design and style is chosen s analyze: – examine in VHDL/Verilog, check for format and synthesizale logic, retail outlet as advanced formats – Use to go through each sub-design + leading level style s sophisticated: – make the design coming from intermediate formats, determine the proper bus size, Use to get the best level style + sub-design with parameters passing in s read: read style formats besides HDL (db, PLA, tc. ) DC Tutorial , 31 DC Tutorial , 32 A Design Features 4 Sights s s i9000 s t s Design View h Design Look at Symbol View Schematic Perspective Hierarchy View T Perspective (No Use) After “read” in all 13 verilog documents in the training directory – you first your Design View DC Training , 33 DC Tutorial , thirty four Symbol Perspective s Schematic View h Select TIME_STATE_MACHINE and double-click on it -&gt, you enter the symbol view of the style Click on the “schematic view” key on the left hand side POWER Tutorial , 35 POWER Tutorial , 36 6th Hierarchy View s Design View Device s t s s

Click the up arrow (left hand side) to go back to style view, doubleclick on TOP, Choose View , &gt, Change View , &gt, Hierarchy – LEADING contains six modules Netlist: read in as a netlist and enhanced to entrance Equation: In VHDL, Verilog, or formula format that may be partially or completely behavioral PLA: Specified in PLA format State Table: Specified in point out table format Y=A+B 010-0 1-101 PLA State Table Netlist Equation DC Training , thirty seven DC Training , 35 Command Windows s dc_shell Commands Set up , &gt, Command Window , s i9000 For more information, – see Design and style Compiler Reference Manual: Principles DC Training , 39

DC Article , forty five Design Attributes s Functioning Environment Sub-menu s Characteristics are ideals you set to manage the optimization process – Select Qualities from the menu s The Attributes menu provide entry to – – – – – – – Set input and output holdups hindrances impediments Set travel strengths collection loads Define subdesigns Choose operating conditions Choose a wire load model Create or modify a clock POWER Tutorial , 41 Arranged design properties that details the internal conditions of a style and the design’s interaction having its surrounding – drive strength on jacks – enough time that alerts arrive upon ports – load powered by output ports

POWER Tutorial , 42 several Optimization Constraints s Design Optimization t Set the goal intended for design marketing – largest delay allowed – greatest area allowed Select Tools , &gt, Design Marketing – Observe Design Compiler Reference Manual: Optimization and Timing Evaluation for more detail s Two set-constraint home windows – Design and style Constraints home window • Goals for region and electric power • Style rules intended by technology library • Test-related restrictions (testability) – Timing Restrictions window • Timing constraints s POWER Tutorial , 43 POWER Tutorial , 44

Finding Problems s i9000 Generate Record s After and before optimization, employ Schematic Perspective and Verify Design to find problems – Generate schematic view – Select Research , &gt, Check Design and style – Bounce to a design and style object • Click on a blunder or warning message in the Design error window • Click on the demonstrate button Analysis , &gt, Report … DC Article , 45 DC Article , 46 Run a Script File t Setup , &gt, Do Script – check out ~/tutorial/appendix_A/*. script – dc_shell&gt, include The Alarm Clock Design and style DC Training , forty seven 8

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