mentor design essay

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To full all aspects of the exercise regarding Deb type flip-flop, TTL and CMOS and familiarize us with the HDL software which can be Mentor Images Essay. This software is competent of creating and simulating a particular design.

As for this kind of assignment you, we are given 4 weeks to complete the assignment. It is compulsory to attend every research laboratory sessions while there is no substitute software to use. Only a certain limit of your energy is given for the use of the software and for that reason designing of circuit is necessary to be finished before going to the lab.

To give students a first hand understanding of the EDA lab and most notably Mentor Design, a powerful instrument in HDL technology.

This kind of assignment permits the students to understand or rather familiarize themselves together with the design circulation of the EDA software and also to fully check out what the application is capable and powerful to accomplish.

Lastly, to arrange the students for the next assignments which in turn uses the similar application.

Introduction D(elay) Flip-Flop (What You Have to Know Initial! )

The D zehengreifer is useful every time a single info bit (1 or 0) is to be stored. An additional inverter to the S-R flip-flop at the R type creates a G flip-flop. The D flip-flop shown under is a changes of the clocked SR zehengreifer.

The D suggestions goes into the S i9000 input as well as the complement from the D input goes to the R type.

If there is a HIGH on the M input every time a clock heartbeat is utilized, the zehengreifer SETs and stores a one. If there is a decreased on the M input when a clock heartbeat is utilized, the zehengreifer RESETs and stores a 0. The facts table listed below summarizes the operations from the positive edge-triggered D zehengreifer. As ahead of, the adverse edge-triggered zehengreifer works a similar except that the falling edge of the time pulse is definitely the triggering border.

InputsD CP(CLK)OutputsQ QComments

you 1 0SET (stores 1)

0 0 1RESET (stores a 0)

The circuit of a D Type zehengreifer has already been directed at us.

We are instructed to construct the given signal using Design Architect ( DA). The constructed circuit is displayed in determine 1 published out using the lab computer printer.

Next, synonymous with the outlet is created applying DA in the menu Assorted followed by Make Symbol. The created symbol is than modified. The modified sign is demonstrated in physique 2 .

Next, Quicksim is activated mainly to invoke forces on the constructed routine and to Trace as well as to examine the output with the circuit through waveforms.

The saved file of the constructed circuit using DA is opened in Quicksim. Firstly, the function TRACE can be used to trace PRE, CLR, CLK, D, Queen, QB. After that a Trace box can look at lower part lower left of the display screen. This is where the simulated waveforms will apprear.

Forces can now be added to all the traced pieces except for Q and QB.

After making the components with all the required ideals, type OPERATE 800.

The waveforms will appear the identical as the necessary waveforms imprinted out in determine 3. (please note that the traced pieces are contained in the waveform results)

As we can easily see clearly in figure a few, the inputs of G are replicated straight to the output Q. Transitions occurs at every positive-edge from the clock. Which means waveforms agree with the requirements mentioned above.

Up coming, an test is done by changing the PRE and CLR to low. Theoretically, an illegitimate output would happen.

The traced end result with the previously mentioned configuration is usually printed in figure four. We can see that whenever both PRE and CLR are low resulting the outcome of Queen and QB to be excessive. QB is defined to be the opposite of Q. Nevertheless this takes place ( both are High) because both PRE and CLR are set to low. It is therefore said that the output gives an illegal procedure. This is because PRE and CLK cannot be started low concurrently.

PRE has to be HIGH to give an output.

Another operation done to the G flip-flop is always to analyze the outcome when the CLK and input D changes simultaneously. We all do this with the addition of force to the CLK and.

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