Microprocessor and Interfacing Essay

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Peripherals and Interfacing FERVOROSO 8255 The parallel input-output port nick 8255 is additionally called because programmable peripheral input-output interface. The Intel’s 8255 is made for use with Intel’s 8-bit, 16-bit and higher capability microprocessors. It includes 24 input/output lines which may be individually programmed in two groups of 12 lines each, or 3 groups of eight lines. The 2 groups of I/O pins happen to be named as Group A and Group B. Each of these two teams contains a subgroup of eight I/O lines referred to as as 8-bit port and another subgroup of four lines or a 4-bit port. Thus Group A contains an 8-bit slot A along with a 4-bit dock.

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C top. PIO 8255 • The port A lines will be identified simply by symbols PA0-PA7 while the port C lines are recognized as PC4-PC7. Likewise, GroupB includes an 8-bit port B, containing lines PB0-PB7 and 4-bit interface C with lower pieces PC0- PC3. The port C top and slot C reduce can be used in combination as an 8-bitport C. • Both the port C are given the same treat. Thus you can have possibly three 8-bit I/O plug-ins or two 8-bit and two 4-bit slots from 8255.

All of these ports can function independently either since input or as result ports. This could be achieved by encoding the components of an internal signup of 8255 called while control expression register ( CWR ). PIO 8255 • The internal block plan and the pin configuration of 8255 are shown in fig. • The 8-bit data tour bus buffer is definitely controlled by the read/write control reasoning. The read/write control logic manages each of the internal and external moves of equally data and control phrases. • RD, WR, A1, A0 and RESET will be the inputs given by the processor to the READ/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional stream is used to interface the 8255 inner data shuttle bus with the external system info bus.

CARITATEVOLE 8255 • This stream receives or perhaps transmits data upon the execution of input or output guidance by the processor. The control words or perhaps status info is also transmitted through the barrier. • The signal information of 8255 are quickly presented the following: • PA7-PA0: These are ten port A lines that acts as both latched outcome or buffered input lines depending upon the control expression loaded in to the control term register. • PC7-PC4: Uppr nibble of port C lines. They may act as either output latches or type buffers lines.

PIO 8255 This dock also can provide for generation of handshake lines in mode 1 or method 2 . • PC3-PC0: They are the lower interface C lines, other particulars are the same because PC7-PC4 lines. • PB0-PB7: These are the eight port B lines which are used because latched outcome lines or perhaps buffered suggestions lines in the same manner as port A. • RD: This can be a input series driven by the microprocessor and should be low to indicate browse operation to 8255. • WR: This can be an input line powered by the processor. A low within this line signifies write procedure. PIO 8255 • CS: This is a chip choose line.

If perhaps this collection goes low, it enables the 8255 to respond to RD and WR alerts, otherwise RD and WR signal will be neglected. • A1-A0: They are the address input lines and are driven by the microprocessor. These lines A1-A0 with RD, WR and CS from the following operations for 8255. These kinds of address lines are used for dealing with any one of the several registers, i actually. e. three ports and a control word signup as succumbed table listed below. • In the event of 8086 systems, if the 8255 is to be interfaced with reduced order info bus, the A0 and A1 buy-ins of 8255 are linked to A1 and A2 correspondingly.

RD 0 0 zero 0 RD 1 1 1 you RD By 1 WR 1 you 1 1 WR 0 0 0 0 WR X 1 CS zero 0 zero 0 CS 0 zero 0 0 CS one particular 0 A1 0 zero 1 1 A1 zero 0 one particular 1 A1 X Times A0 0 1 zero 1 A0 0 1 0 you A0 Back button X Suggestions (Read) circuit Port A to Info bus Port B to Data shuttle bus Port C to Data bus CWR to Info bus Output (Write) circuit Data coach to Port A Data shuttle bus to Slot B Data bus to Port C Data bus to CWR Function Data bus tristated Data tour bus tristated Control Word Sign-up PIO 8255. • D0-D7: These are the data bus lines those hold data or control word to/from the microprocessor. • RESET: A logic at the top of this collection clears the control phrase register of 8255. Most ports happen to be set while input slots by default after reset.

Block Diagram of 8255 (Architecture) ( cont.. ) • 1 . 2 . 3. some. • Very low 40 buy-ins of four groups. Data bus barrier Read Create control common sense Group A and Group B settings Port A, B and C Info bus barrier: This is a tristate bidirectional buffer utilized to interface the 8255 to system databus. Data is usually transmitted or perhaps received by buffer about execution of input or perhaps output teaching by the PROCESSOR.

Control term and position information are usually transferred through this device. • Prevent Diagram of 8255 (Architecture) ( cont.. ) Read/Write control reasoning: This unit accepts control signals ( RD, WR ) and also inputs coming from address coach and issues commands to individual group of control blocks ( Group A, Group B). • It has the subsequent pins. a) CS – Chipselect: A low on this PIN NUMBER enables the communication among CPU and 8255. b) RD (Read) – A decreased on this pin number enables the CPU to learn the data inside the ports or the status term through info bus buffer. • Obstruct Diagram of 8255 (Architecture) ( cont.. ) WR ( Write ): A low on this pin number, the CENTRAL PROCESSING UNIT can create data on to the ports or on to the control register through the data tour bus buffer. ) RESET: A high on this flag clears the control sign-up and all ports are going the suggestions mode e) A0 and A1 ( Address hooks ): These types of pins in conjunction with RD and WR buy-ins control the selection of one of the 3 ports. • Group A and Group B handles: These stop receive control from the CENTRAL PROCESSING UNIT and problems commands with their respective plug-ins. c) Prevent Diagram of 8255 (Architecture) ( cont.. ) • Group A – PENNSYLVANIA and PCU ( PC7 -PC4) • Group M – PCL ( PC3 – PC0) • Control word register can only be written into no examine operation from the CW register is allowed. a) Dock A: This has an almost 8 bit latched/buffered O/P and 8 tad input latch. It can be set in three or more modes – mode zero, mode 1, mode 2 . b) Dock B: This has an 8 bit latched / buffered O/P and 8 little input latch.

It can be set in setting 0, mode1. Block Picture of 8255 (Architecture). c) Port C: This has an 8 little latched suggestions buffer and 8 bit out put latched/buffer. This port can be divided into two 4 little bit ports and is used as control indicators for port A and port W. it can be set in function 0. Settings of Procedure of 8255 (cont.. ) • They are two simple modes of operation of 8255.

I/O mode and Bit Set-Reset mode (BSR). • In I/O setting, the 8255 ports are programmable I/O ports, although in BSR mode just port C (PC0-PC7) may be used to set or perhaps reset their individual port bits. • Under the I/O mode of operation, further more there are three modes of operation of 8255, so as to support various kinds of applications, mode 0, mode 1 and mode installment payments on your Modes of Operation of 8255 (cont.. ) • BSR Setting: In this method any of the 8-bits of port C can be set or perhaps reset according to D0 from the control term. The bit to be set or reset can be selected by simply bit select flags D 3, D2 and D one of the CWR as given in table. I/O Ways: a) Function 0 ( Basic I/O mode ): This function is also named as standard input/output function.

This setting provides straightforward input and output features using each one of the three jacks. Data may be simply examine from and written to the input and output slots respectively, following appropriate initialisation. D3 zero 0 zero 0 one particular 1 1 1 D2 0 zero 1 1 0 0 1 one particular D1 zero 1 zero 1 0 1 0 1 Picked bits of port C D0 D1 D2 D3 D4 D5 D6 D7 BSR Mode: CWR Format PA 8 2 5 5 PCU PCL PA6 – PA7 PC4 – PC7 PC0-PC3 PB PB0 – PB7 eight 2 5 5 PENNSYLVANIA PCU PCL PB PENNSYLVANIA PC PB0 – PB7 All Outcome Port A and Interface C performing as O/P.

Port B acting because I/P Mode 0 Ways of Procedure of 8255 (cont.. ) • 1 ) The salient features of this kind of mode happen to be as the following: Two 8-bit ports ( port A and interface B )and two 4-bit ports (port C upper and lower ) can be obtained. The two 4-bit ports could be combinedly applied as a third 8-bit port. Any slot can be used as an input or result port. End result ports are latched. Type ports are certainly not latched.

No greater than four jacks are available to ensure that overall of sixteen I/O configuration are conceivable. All these modes can be picked by encoding a signup internal to 8255 generally known as CWR. 2 . 3. 4. • Modes of Operation of 8255 (cont.. • The control word signup has two formats. The first formatting is valid for I/O modes of operation, i. e. ways 0, function 1 and mode two while the second format can be valid to get bit set/reset (BSR) function of operation. These forms are proven in following fig.

D7 1 D6 X D5 X D4 X D 3 D2 D1 D0 0- Reset 0-for BSR function Bit choose flags D3, D2, D1 are via 000 to 111 intended for bits PC0 TO PC71- Set I/O Mode Control Word Register Format and BSR Mode Control Expression Register Formatting PA3 PA2 PA1 PA0 RD CS GND A2 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 two 3 5 5 6th 7 eight 9 15 11 doze 13 13 15 18 17 18 19 20 0 39 38 thirty seven 36 35 34 33 32 31 30 30 28 28 26 25 24 twenty-three 22 twenty one PA4 PA5 PA6 PA7 WR Reset D0 D1 D2 D 3 D4 D5 D6 D7 Vcc PB7 PB6 PB5 PB4 PB3 8255A 8255A Pin Construction = D0-D7 CS RESET 8255A A0 A1 RD PA0-PA7 PC4-PC7 PC0-PC3 PB0-PB7 Vcc WR GND Signals of 8255 3 Group A control 1 D0-D7 Data bus Buffer almost 8 bit int data shuttle bus 4 Group A Slot A(8) PA0-PA7 Group A Port C upper(4) Group B Port C Lower(4) PC7-PC4 PC0-PC3 2 RD WR A0 A1 RESET CS Block Diagram of 8255 READ/ WRITE Control Logic Group B control PB7-PB0 Group B Interface B(8) D7 D6 D5 Mode for Port A D4 PA D 3 PC U D2 Mode for PB D1 PB D0 PC T Mode Established flag 1- active 0- BSR method Group – A 1 Suggestions PC u 0 Output 1 Input PA 0 Output 00 – method 0 Mode 01 – mode you Select of PA 10 – method 2 Group – N PCL PB Mode Select 1 Input 0 End result 1 Input 0 Result 0 mode- 0 you mode- you Control Term Format of 8255 Settings of Operation of 8255 (cont.. ) b) Mode 1: ( Strobed input/output mode ) In this mode the handshaking control the input and output action of the particular port. Slot C lines PC0-PC2, provide strobe or perhaps handshake lines for dock B. This group which include port M and PC0-PC2 is called since group M for Strobed data input/output.

Port C lines PC3-PC5 provide strobe lines pertaining to port A. This group including port A and PC3-PC5 by group A. Thus slot C is usually utilized for making handshake indicators. The prominent features of method 1 are listed as follows: Modes of Operation of 8255 (cont.. ) 1 ) 2 . three or more. 4. Two groups – group A and group B are available for strobed data. Each group contains a single 8-bit data I/O slot and one particular 4-bit control/data port.

The 8-bit info port may be either used as output and input port. The inputs and outputs the two are latched. Out of 8-bit port C, PC0-PC2 prefer generate control signals to get port W and PC3-PC5 are used to generate control indicators for dock A. this individual lines PC6, PC7 can be utilized as impartial data lines.

Modes of Operation of 8255 (cont.. ) • The control signals for the groups in input and output modes are explained as follows: Type control sign definitions (mode 1 ): • STB( Strobe type ) – If this lines falls to reasoning low level, the data available at 8-bit input dock is packed into suggestions latches. • IBF ( Input stream full ) – In the event that this transmission rises to logic one particular, it indicates that data has become loaded into latches, my spouse and i. e. functions as an acknowledgement. IBF is set with a low about STB and is reset by the rising edge of RD input.

Modes of Operation of 8255 (cont.. ) • INTR ( Disrupt request ) – This active large output sign can be used to interrupt the CENTRAL PROCESSING UNIT whenever a great input system requests the service. INTR is set by a high STB pin and a high for IBF pin number. INTE is usually an internal banner that can be controlled by the bit set/reset mode of either PC4 (INTEA) or PC2(INTEB) because shown in fig. • INTR can be reset with a falling edge of RD input.

Hence an external input device can be request the service from the processor simply by putting the info on the shuttle bus and sending the strobe signal. Modes of Procedure of 8255 (cont.. End result control transmission definitions (mode 1): • OBF (Output buffer total ) – This position signal, whenever falls to low, indicates that CENTRAL PROCESSING UNIT has crafted data towards the specified end result port. The OBF zehengreifer will be set by a increasing edge of WR sign and totally reset by a low going advantage at the ACK input. • ACK ( Acknowledge insight ) – ACK transmission acts as a great acknowledgement to become given by a great output unit.

ACK signal, whenever low, informs the CPU the fact that data transported by the CENTRAL PROCESSING UNIT to the end result device through the port is definitely received by the output system. Modes of Operation of 8255 (cont.. ) • INTR ( Interrupt demand ) – Thus an output signal that can be used to interrupt the CPU for the output system acknowledges the data received in the CPU. INTR is set once ACK, OBF and EJ are 1 ) It is totally reset by a dropping edge on WR type.

The INTEA and INTEB flags happen to be controlled by the little bit set-reset function of PC 6and PC2 respectively. one particular 0 one particular 0 Type control sign definitions in Mode 1 1/0 Times X Back button 1 Times X Back button X 1 1 X D7 D6 D5 D4 D3 D2 D1 D0 1 – Input 0 – End result For PC6 – PC7 PA0 – PA7 INTEA PC4 PC5 STBA IBFA D7 D6 D5 D4 D3 D2 D1 D0 PB0 – PB7 INTEB PC 2 PC1 STBB IBFB PC3 RD PC6 – PC7 INTRA I/O PC0 INTR A Method 1 Control Word Group A I/P RD Function 1 Control Word Group B I/P STB IBF INTR RD DATA via Peripheral Function 1 Strobed Input Data Transfer WR OBF INTR ACK Data OPERATIVE to Slot Mode one particular Strobed Data Output Outcome control sign definitions Method 1 you 0 one particular 0 1/0 X Back button X one particular X X X By 1 zero X D7 D6 D5 D4 D3 D2 D1 D0 you – Insight 0 – Output Intended for PC4 – PC5 PA0 – PA7 INTEA PC7 PC6 OBF ACKA D7 D6 D5 D4 D3 D2 D1 D0 PB0 PB7 INTEB PC PC2 1 OBFB ACKB PC3 WR PC4 – PC5 PC0 INTRA I/O INTRB Mode you Control Word Group A Mode you Control Phrase Group W Modes of Operation of 8255 (cont.. ) • Mode a couple of ( Strobed bidirectional I/O ): This kind of mode of operation of 8255 is likewise called since strobed bidirectional I/O. This mode of operation supplies 8255 with an additional features for conntacting a peripheral device with an 8-bit data bus.

Handshaking signals are provided to maintain correct data movement and sync between the data transmitter and receiver. The interrupt era and other capabilities are similar to mode 1 . • In this mode, 8255 is known as a bidirectional 8-bit port with handshake signs. The RD and WR signals determine whether the 8255 is going to work as an input dock or result port.

Methods of Operation of 8255 (cont.. ) • 1 . 2 . 3. 4. a few. The Salient features of Method 2 of 8255 are listed as follows: The single 8-bit port in group A is available. The 8-bit interface is bidirectional and additionally a 5-bit control port can be bought. Three I/O lines are available at port C. ( PC2 – PC0 ) Inputs and outputs are both latched.

The 5-bit control slot C (PC3-PC7) is used intended for generating / accepting handshake signals to get the 8-bit data transfer in port A. Modes of Operation of 8255 (cont.. ) • Control transmission definitions in mode two: • INTR – (Interrupt request) As with mode one particular, this control signal is definitely active large and is accustomed to interrupt the microprocessor to request transfer from the next info byte to/from it. This signal can be used for input ( go through ) and output ( write ) operations. • Control Signals for Output operations: • OBF ( Output barrier full ) – This signal, when ever falls to low level, signifies that the PROCESSOR has created data to port A. Modes of Operation of 8255 (cont.. ) ACK ( Recognize ) This control insight, when declines to reasoning low level, appreciates that the past data byte is received by the vacation spot and next octet may be directed by the processor.

This transmission enables the interior tristate buffers to send the next data octet on port A. • INTE1 ( A flag associated with OBF ) This is often controlled by bit set/reset mode with PC6. • Control signs for input operations: • STB (Strobe input ) A low within this line is used to strobe in the data into the input latches of 8255. Methods of Operation of 8255 (cont.. ) • IBF ( Input buffer full ) When the data is loaded in to input buffer, this ignal rises to logic ‘1′. This can be employed as an acknowledge that the data has been received by receiver. • The waveforms in fig show the operation in Method 2 pertaining to output and also input interface. • Be aware: WR need to occur before ACK and STB must be activated just before RD.

WR OBF INTR ACK STB IBF Info bus RD Mode two Bidirectional Data Data via 8085 Info towards 8255 Modes of Operation of 8255 (cont.. ) • The following fig shows a schematic diagram containing an 8-bit bidirectional port, 5-bit control port and the relation of INTR with the control pins. Port B can be going Mode 0 or you with interface A( Group A ) is in Method 2 . Method 2 is usually not available for port B. The following fig shows the control term. • The INTR moves high as long as either IBF, INTE2, STB and RD go excessive or OBF, INTE1, ACK and WR go large. The dock C could be read to be aware of the status of the peripheral device, with regards to the control signals, making use of the normal I/O instructions. D7 1 D6 1 D5 X D4 X D 3 X D2 1/0 D1 1/0 D0 1/0 1/0 mode Slot A setting 2 Slot B method 0-mode 0 1- function 1 PC2 – PC0 1 – Input zero – Result Port W 1- I/P 0-O/P Mode 2 control word PC3 PA0-PA7 INTR INTE you PC7 PC6 OBF ACK STB IBF 3 I/O INTE two RD WR PC4 PC5 Mode a couple of pins

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