the use of a dual material gateway dmg
Today’s cellular electronics community is motivated by the products which should inherently provide high-speed, high performance and low leakage. Such an expanding demand an excellent source of performance equipment catalyzes the aggressive scaling of the transistors below 22 nm. Yet , the constant miniaturization of transistor measurements has ended in the increased static electricity dissipation because of the leakage current at an appalling rate.
Moreover, the physical constraints in recognizing ultra-scaled sizes such as instant doping users, lithography position and the increased short route effects due to inefficient door control include restricted the realization with the ultra-scaled time-honored planar transistors. All these elements have outdistanced the conventional single gate planar transistors therefore shifting major of the experts towards the multiple-gate transistors which will consume the minimum real-estate on the semiconductor wafer along with better performance by providing useful gate control. In this current realm, 3D topologies such as Gate-all-around (GAA) nanowires (NW) are considered as the most promising ultimate short channel system for foreseeable future technology [1]-[4].
However the effective drive current that may be taken out from a single nanowire is pretty low and thus, needs to be piled into arrays consuming the valuable chip area thereby countering the benefit of the scaled dimensions [5],[6]. Moreover, this kind of effective gateway control brings about a significant terme conseillé of the funnel region valence band with all the drain conduction band in the OFF-state plan triggering the lateral band to strap tunneling (L-BTBT) of electrons from the channel to the drain [4][6-16]. Nevertheless , the conventional transverse-BTBT (T-BTBT) caused gate activated drain seapage (GIDL) current arises because of the tunneling in the electrons in the valence strap to the leasing band in the gate-drain overlap region throughout the mechanism of band to band tunneling (BTBT) and trap assisted tunneling(TAT) and it is dominant in particular negative gate bias [4][17],[18].
Therefore , the expedition of FETs with an increased output travel current from 3D topologies along with a better ION/IOFF percentage has resulted in the invention from the silicon nanotubes with primary shell gate stack [19-27]. Such a nanotube architecture provides the best possible electrostatic gate control which not merely provides defenses to the short channel results but likewise results in a better drive current due to the effective volume inversion compared to the nanowires along with the effective utilization of the real-estate [19-22]. Nevertheless , this supreme gate control in the NT architecture brings about an improved L-BTBT mechanism due to the presence of the primary gate [27]. Therefore , the enhanced L-BTBT in nanotube increases their particular OFF-state current degrading their ION/IOFF proportion Moreover, the L-BTBT much more pronounced in the scaled proportions hindering their scaling towards the future technology nodes and making their very own usage not practical for high end computing as well as low electrical power applications. Therefore, L-BTBT needs to be mitigated which problem has been overlooked right up until date.
Therefore , with this work, we all propose conditions dual materials gate (DMG) in both the core along with outer gate to prevent the enhanced L-BTBT component in NTFETs to facilitate their scaling for future technology nodes. The DMG has been implemented before for conventional lateral funnel devices just like planar bulk and SOI MOSFET, TFETs, Junctionless FETs and nanowire architectures [28-37] and had recently been experimentally realized[28][31][36][37] for improving the transistor’s overall performance. However , to get such conventional lateral funnel devices, the fabrication of a DMG
